1. Field of the Invention
The present invention relates to an all-digital phase-locked loop (ADPLL) and a loop bandwidth calibration method used on the same.
2. Description of the Prior Art
A phase-locked loop (PLL) is an electronic control system that generates a signal that has a fixed relation to the phase of a reference signal. A phase-locked loop circuit responds to both the frequency and the phase of the input signals, and automatically raises or lowers the frequency of a controlled oscillator until it is matched to the reference signal in both frequency and phase. A conventional analog PLL includes a phase detector, a voltage-controlled oscillator (VCO), and a feedback path for feeding output signals of the VCO back to an input terminal of the phase detector so as to raise or lower a frequency of input signals of the analog PLL. Therefore, the frequency of the analog PLL may always catch up with a reference frequency of a reference signal applied by the phase detector, i.e., the frequency of the input signals of the analog PLL is always locked by the reference frequency of the reference signal. Moreover, a frequency divider is conventionally applied on the feedback path so that multiples of the reference frequency may always be retrieved. A low-pass filter is conventionally connected after the phase detector so that noises staying at higher frequencies may thus be filtered.
As known by those skilled in the art, the analog PLL easily has errors (or even error propagation) since said analog PLL uses analog operations and analog elements. Therefore, digital phase-locked loops (DPLL), which utilize a counter with a variable divisor on the feedback path, are proposed for relieving the errors with the partial aid of digital operations and digital elements, and moreover, an all-digital phase-locked loop (ADPLL) may significantly helps in area reduction and process migration. For example, a digital-controlled oscillator (DCO) may be used for in replace of the conventionally used VCO, which is an analog element. A phase detector may also be replaced with a time-to-digital converter. Therefore, the usage of the ADPLL is becoming a trend in radio communications.